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| 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6CV857L PLL Clock Driver for 2.5V DDR-SDRAM Memory Product Features PLL clock distribution optimized for Double Data Rate SDRAM applications. Distributes one differential clock input pair to ten differential clock output pairs. Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 Input PWRDWN: LVCMOS Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2 External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the clock input. Operates at AVDD = 2.5V for core circuit and internal PLL, and VDDQ = 2.5V for differential output drivers Available Packages: Plastic 48-pin TSSOP Product Description PI6CV857L PLL clock device is developed for registered DDR DIMM applications This PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels. Package options include plastic Thin Shrink Small-Outline Package (TSSOP).The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock outputs (FBOUT,FBOUT) . The clock outputs are controlled by the input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), the 2.5V LVCMOS input (PWRDWN) and the Analog Power input (AVDD). When input PWRDWN is low while power is applied, the input receivers are disabled, the PLL is turned off and the differential clock outputs are 3-stated. When the AVDD is strapped low, the PLL is turned off and bypassed for test purposes. When the input frequency falls below a suggested detection frequency that is below the operating frequency of the PLL, the device will enter a low power mode. An input frequency detection circuit will detect the low frequency condition and perform the same low power features as when the PWRDWN input is low. The PLL in the PI6CV857L clock driver uses the input clocks (CLK, CLK) and the feedback clocks (FBIN,FBIN) to provide high-performance, low-skew, low-jitter output differential clocks (Y[0:9], Y[0:9]). The PI6CV857L is also able to track Spread Spectrum Clocking for reduced EMI. Y0 Block Diagram/Pin Configuration Y0 Y1 PLL Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Powerdown and Test Logic Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 FBOUT FBOUT CLK CLK FBIN FBIN PWRDWN AVDD GND Y0 Y0 VD D Q Y1 Y1 GND GND Y2 Y2 VD D Q VD D Q CLK CLK VD D Q AV D D AG N D GND Y3 Y3 VD D Q Y4 Y4 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48-Pin A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND Y5 Y5 VD D Q Y6 Y6 GND GND Y7 Y7 VD D Q P W R DW N FBIN FBIN VD D Q FBOUT FBOUT GND Y8 Y8 VD D Q Y9 Y9 GND 1 PS8543 06/11/01 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6CV857L PLL Clock Driver for 2.5V DDR-SDRAM Memory Pinout Table Pin Name CLK CLK Yx Yx FBOUT FBOUT FBIN FBIN PWRDWN VDDQ AVDD AGND GND Pin No. 13 14 3,5,10,20,22,27,29,39,44,46 2,6,9,19,23,26,30,40,43,47 32 33 36 35 I 37 4,11,12,15,21,28,34,38,45 16 17 1,7,8,18,24,25,31,41,42,48 Power O I/O Type I Reference Clock input Clock outputs. Complement Clock outputs. Feedback output, and Complement Feedback Output Feedback output, and Complement Feedback Output Power down and output disable for all Yx and Yx outputs. When PWRDWN = 0, the part is powered down and the differential clock outputs are disabled to a 3- state. When PWRDWN = 1, all differential clock outputs are enabled and run at the same frequency as CLK. Power Supply for I/O. Analog /core power supply. AVDD can be used to bypass the PLL for testing purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. Analog/core ground. Provides the ground reference for the analog/core circuitry Ground De s cription Ground Function Table Inputs AVDD GND GND X X 2.5V(nom) 2.5V(nom) 2.5V(nom) G H H L L H H X CLK L H L H L H <20 MHz (1) CLK H L H L H L Y L H Z Z L H Z Y H L Z Z H L Z Outputs FBO UT L H Z Z L H Z FBO UT H L Z Z H L Z Bypassed/off Bypassed/off off off on on off PLL State Notes: For testing and power saving purposes, PI6CV857L will power down if the frequency of the reference inputs CLK, CLK is well below the operating frequency range. The maximum power down clock frequency is below 20 MHz. For example, PI6CV857L will be powered down when the CLK,CLK stop running. Z = High impedance X = Dont care 2 PS8543 06/11/01 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6CV857L PLL Clock Driver for 2.5V DDR-SDRAM Memory Absolute Maximum Ratings (Over operating free-air temperature range) Symbol VDDQ, AVDD VI VO Tstg Parame te r I/O supply voltage range and analog/core supply voltage range Input voltage range Output voltage range Storage temperature M in. 0.5 0.5 0.5 65 M ax. 3.6 VDDQ 0.5 150 V oC Units Note: Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Timing Requirements (Over recommended operating free-air temperature) Symbol D e s cription O perating clock frequency(1,2) Application clock frequency(3) AVDD, VDDQ = 2.5V 0.2V M in. 60 95 40 M ax. 170 170 60 100 Units fCK tDC tSTAB MHz % s Input clock duty cycle PLL stabilization time after powerup Notes: 1. The PLL is able to handle spread spectrum induced skew. 2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not required to meet the other timing parameters. (Used for low-speed debug). 3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters. 3 PS8543 06/11/01 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6CV857L PLL Clock Driver for 2.5V DDR-SDRAM Memory DC Specifications Symbol AVDD VDDQ VIL VIH VOH VOL VIX VOX VIN VID VOD TA Recommended Operating Conditions Parame te r Analog/core supply voltage O utput supply voltage Low- level input voltage for PWRDWN pin High- level input voltage for PWRDWN pin High- level output voltage Low- level output voltage Input differential- pair crossing voltage O utput differential- pair crossing voltage at the DRAM clock input Input voltage level Input differential voltage between CK and CK O utput differential voltage between Y[n] &Y[n] and FBO UT & FBO UT O perating free air temperature M in. 2.3 2.3 0.3 1.7 1.8 0 (VDDQ/2) 0.2 (VDDQ/2) 0.2 0.3 0.36 0.7 0 Nom. 2.5 2.5 M ax. 2.7 2.7 0.7 VDDQ +0.3 VDDQ 0.5 (VDDQ/2) +0.2 (VDDQ/2) +0.2 VDDQ +0.3 VDDQ +0.6 VDDQ +0.6 70 C V Units Electrical Characteristics Parame te r VIK II All inputs CK , FBIN PWRDWN IDDQ Dynamic supply current of VDDQ Static supply current Dynamic supply current of AVDD IADD Static supply current CK and CK FBIN and FBIN Te s t Conditions II = 18mA VI = VDDQ or GND VI = VDDQ or GND VDD = 2.7V CK & CK <20 MHz or PWRDWN = Low (1) VDD = 2.7V CK & CK <20 MHz or PWRDWN = Low (1) VI = VDD or GND 2.5V 2.0 2.7V AVDD, VDDQ 2.3V M in. Typ. M ax. 1.2 10 300 100 12 100 3.0 Units V A mA A mA A pF CI Note: 1. The maximum power-down clock frequency is below 20 MHz. 4 PS8543 06/11/01 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6CV857L PLL Clock Driver for 2.5V DDR-SDRAM Memory AC Specifications Parame te r tjit(cc) t(q) tsk(o) tjit(per) tjit(hper) tsl(i) tsl(o) Switching characteristics over recommended operating free-air temperature range (unless otherwise noted)( See Figure 1 & 2 ) De s cription Cycle- to- cycle jitter Static phase offset(1) O utput clock skew Period jitter Half- period jitter Input clock slew rate(2) O utput clock slew rate(2) D iagram see Figure 3 see Figure 4 see Figure 5 see Figure 6 see Figure 7 see Figure 8 see Figure 8 AVCC, VDDQ = 2.5V 0.2V M in. 75 50 0 Nom. M ax 75 50 100 75 100 1.0 1.0 75 100 2.0 2.0 Units ps V/ns The PLL on the PI6CV857L is capable of meeting all the above parameters while supporting SSC synthesizers with the following parameters(3). SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth Phase angle Notes: 1. Static Phase offset does not include Jitter. 2. The slew rate is determined from the IBIS model with test load shown in Figure1. 3. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification. 30.00 0.00 2 50.00 0.50 kHz % MHz 0.031 degrees 5 PS8543 06/11/01 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6CV857L PLL Clock Driver for 2.5V DDR-SDRAM Memory VDD Z=60 DDR SDRAM R=120 Z=60 DDR SDRAM PI6CV857 Figure 1. IBIS Model Output Load VDDQ/2 Z= 60 R = 10 C = 14pF Z= 50 R = 50 Z= 60 -VDDQ/2 C = 14pF R = 50 -VDDQ/2 GND R = 10 Z= 50 GND PI6CV857 -VDDQ/2 SCOPE Figure 2. Output Load Test Circuit 6 PS8543 06/11/01 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6CV857L PLL Clock Driver for 2.5V DDR-SDRAM Memory Yx,FBOUT Yx,FBOUT t cycle n t jit(cc) = t cycle n - t cycle n+1 t cycle n+1 Figure 3. Cycle-to-Cycle Jitter CK CK FBIN FBIN t( )n t( n=N ) n+1 t 1 = t( )n (N is a large number of samples) N Figure 4. Static Phase Offset Yx Yx Yx, FBOUT Yx, FBOUT t sk(o) Figure 5. Output Skew 7 PS8543 06/11/01 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6CV857L PLL Clock Driver for 2.5V DDR-SDRAM Memory Yx, FBOUT Yx, FBOUT t cycle n Yx, FBOUT Yx, FBOUT 1 fO t jit(per) = t cycle n 1 fO Figure 6. Period Jitter Yx, FBOUT Yx, FBOUT t half period n 1 fO t n+1 half period t jit(hper) = t half period n 1 2*f O Figure 7. Half-Period Jitter 80% 80% V ID Clock Inputs and Outputs 20% 20% t sl(i), t sl(o) t sl(i), t sl(o) Figure 8. Input and Output Slew Rates 8 PS8543 06/11/01 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 PI6CV857L PLL Clock Driver for 2.5V DDR-SDRAM Memory Packaging Mechanical: 48-Pin TSSOP 48 .236 .244 6.0 6.2 1 .488 12.4 .496 12.6 .047 1.20 Max SEATING PLANE .004 0.09 .008 0.20 0.45 .018 0.75 .030 .319 BSC 8.1 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS .0197 BSC 0.50 .007 .010 0.17 0.27 .002 .006 0.05 0.15 Ordering Information Orde ring Code PI6CV857LA Package Name A48 Package Type 48- pin, 240- mil wide TSSO P Pericom Semiconductor Corporation 2380 Bering Drive San Jose, CA 95131 1-800-435-2336 Fax (408) 435-1100 http://www.pericom.com 9 PS8543 06/11/01 |
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